1. Field of the Invention
The present invention relates in general to digital/analog converters, and more particularly to a digital/analog converter in which input digital data is divided into higher-order bits and lower-order bits and the divided higher and lower-order bits are processed by current and resistor array manners, respectively, so that a digital/analog conversion operation can be performed at a high speed and a high resolution, and an error resulting from a process deviation is automatically compensated by a current compensation circuit so that an integration degree of a semiconductor device can be enhanced.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional digital/analog converter. As shown in this drawing, the conventional digital/analog converter comprises a voltage divider 1 for dividing a difference between top and bottom reference voltages V.sub.RT and V.sub.RB into 2.sup.N steps if the bits number of an input digital signal is N. To this end, the voltage divider 1 includes a string of 2.sup.N resistors R1-R2.sup.N connected in series between the top and bottom reference voltages V.sub.RT and V.sub.RB.
The conventional digital/analog converter also comprises a decoder 3 for decoding the N-bit input digital signal into a 2.sup.N -bit signal and outputting the decoded 2.sup.N -bit signal to a divided-voltage selector 2. The divided-voltage selector 2 is adapted to selectively output the voltages divided into the 2.sup.N steps by the voltage divider 1 in response to the output signal from the decoder 3. To this end, the divided-voltage selector 2 includes 2.sup.N -1 electronic switches S1-S2.sup.N -1.
Further, the conventional digital/analog converter comprises an output buffer 4 for buffering an output voltage from the divided-voltage selector 2 and outputting the buffered voltage.
The operation of the conventional digital/analog converter with the above-mentioned construction will hereinafter be described.
If the bits number of the input digital signal is N, in the voltage divider 1, the difference V.sub.RT -V.sub.RB between the top and bottom reference voltages V.sub.RT and V.sub.RB is divided into the 2.sup.N steps by the 2.sup.N resistors R1-R2.sup.N connected in series therebetween. In this case, a voltage across each of the resistors R1-R2.sup.N is (V.sub.RT -V.sub.RB)/2.sup.N [V].
Each of 2.sup.N -1 nodes is formed between adjacent ones of the resistors R1-R2.sup.N in the voltage divider 1 and connected to one terminal of a corresponding one of the 2.sup.N -1 electronic switches S1-S2.sup.N -1 in the divided-voltage selector 2, the other terminals of which are connected in common to a non-inverting input terminal of an operational amplifier in the output buffer 4. The decoder 3 decodes the N-bit input digital signal into the 2.sup.N -bit signal and outputs the decoded 2.sup.N -bit signal as a switching control signal to the electronic switches S1-S2.sup.N -1.
The electronic switches S1-S2.sup.N -1 in the divided-voltage selector 2 are turned on/off in response to the 2.sup.N -bit signal from the decoder 3 to selectively output the voltages divided into the 2.sup.N steps by the voltage divider 1. Then, the output buffer 4 amplifies the output voltage from the divided-voltage selector 2 by a desired level and outputs the amplified voltage.
However, the above-mentioned conventional digital/analog converter has a disadvantage in that the resistor string and the switch group are increased in size as a resolution of an output voltage Vo becomes higher, resulting in an increase in the chip size and consumption power. Also, when the resistor string has no matching, the resolution is reduced.